VLSI Design 3151105 Syllabus Download With Weightage

VLSI Design 3151105 Syllabus is a term that refers to Electronics and Communication Department covers this subject This year, this Subject is covered in the 5th Semester.

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1

Introduction:

Overview of VLSI design methodology, VLSI design flow, Design
hierarchy, Concept of regularity, Modularity, and Locality, VLSI design
style, Design quality, package technology, introduction to FPGA and
CPLD, computer aided design technology.

6
2

Fabrication of MOSFET :

Introduction, Fabrication Process flow: Basic steps, C-MOS n-
WellProcess, Layout Design rules, full custom mask layout design.

6
3

MOS Transistor:

The Metal Oxide Semiconductor (MOS) structure, The MOS System
underexternal bias, Structure and Operation of MOS transistor, MOSFET
Current-Voltage characteristics, MOSFET scaling and small-geometry
effects, MOSFETcapacitances

11
4

MOS Inverters – Static Characteristics:

Introduction, Resistive load Inverter, Inverter with n-type MOSFET
load(Enhancement and Depletion type MOSFET load), CMOS Inverter

9
5

MOS Inverters Switching characteristics and Interconnect Effects:

Introduction, Delay-time definitions, Calculation of Delay times, Inverter
designwith delay constraints, Estimation of Interconnect Parasitic,
Calculation ofinterconnect delay, Switching Power Dissipation of CMOS
Inverters

11
6

Combinational MOS Logic Circuits:

Introduction, MOS logic circuits with Depletion nMOS Loads, CMOS
logiccircuits, Complex logic circuits, CMOSTransmission Gates (TGs)

5
7

Sequential MOS Logic Circuits:

Introduction, Behavior of Bistable elements, The SR latch circuit,
Clockedlatch and Flip-flop circuit, CMOS D-latch and Edge-triggered
flip-flop

4
8

Dynamic Logic Circuits:

Introduction, Basic Principles of pass transistor circuits, Voltage
Bootstrapping, Synchronous Dynamic Circuit Techniques, CMOS
DynamicCircuit Techniques, High-performance Dynamic CMOS circuits

7
9

Chip I/P and O/P Circuits:

On chip Clock Generation and Distribution, Latch –Up and its Prevention

3
10

Chip I/P and O/P Circuits:

On chip Clock Generation and Distribution, Latch –Up and its Prevention

4
11

FinFET Device:

Introduction (Need of FinFET device), structure,
Comparison between FinFET and Planar MOSFET (gm, gds, leakage
current, DIBL, Subthreshold Slope)

4

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