Testing and Verification 3171111 syllabus Download
Testing and Verification 3171111 is presented in the 7th semester of the EC department.
Sr. No.
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Content
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Total Weightage
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| 1 |
Introduction:Importance of Testing, Testing during VLSI Lifecycle, Challenges in VLSI Testing, Levels of Abstraction in VLSI Testing, Historical Review of VLSI Test Technology. |
13 |
| 2 |
Design and Testability:Introduction, Testability Analysis, Design for Testability Basics, Scan Cell Designs, Scan Architectures, Scan Design Rules, Scan Design Flow, Special purpose Scan Designs, RTL Design for Testability |
21 |
| 3 |
Logic and Fault Simulation:Introduction, Simulation Models, Logic Simulation, Fault Simulation |
15 |
| 4 |
Verification:Importance of verification, Verification plan, Verification flow, Levels of verification, Verification methods and languages |
8 |
| 5 |
Verification Techniques using System Verilog:Linting, Simulation, Verification Intellectual Property, Waveform Viewers, Code Coverage, Functional Coverage, Verification Language Technologies, Assertions, Revision Control, Issue Tracking, Metrics |
13 |
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