Testing and Verification 3171111 syllabus Download
Testing and Verification 3171111 is presented in the 7th semester of the EC department.
Importance of Testing, Testing during VLSI Lifecycle, Challenges in VLSI Testing, Levels of Abstraction in VLSI Testing, Historical Review of VLSI Test Technology.
Design and Testability:
Introduction, Testability Analysis, Design for Testability Basics, Scan Cell Designs, Scan Architectures, Scan Design Rules, Scan Design Flow, Special purpose Scan Designs, RTL Design for Testability
Logic and Fault Simulation:
Introduction, Simulation Models, Logic Simulation, Fault Simulation
Importance of verification, Verification plan, Verification flow, Levels of verification, Verification methods and languages
Verification Techniques using System Verilog:
Linting, Simulation, Verification Intellectual Property, Waveform Viewers, Code Coverage, Functional Coverage, Verification Language Technologies, Assertions, Revision Control, Issue Tracking, Metrics
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